Power supply voltage is provided through power supply circuits to external loads. Power supply circuits generally have a configuration of a high side power MOS transistor and a low side power MOS transistor coupled in series. The high side power MOS transistor may be coupled between a supply node for receiving a supply voltage and an output node for providing the supply voltage to external loads, and the low side power MOS transistor is coupled between the output node and a reference node for receiving a reference voltage that is lower than the supply voltage. These two power MOS transistors may be turned on or off to selectively deliver the supply voltage to the external loads.
FIG. 1 shows a conventional driver circuit 10 for driving a high side power PMOS transistor 11. As shown in FIG. 1, the high side power PMOS transistor 11 is coupled between a supply node 12 and an output node 13, and a gate of the high side power PMOS transistor 11 is coupled to a control node 14 to receive an operation signal Vop. Further, a resistor 15 is coupled between the gate of high side power PMOS transistor 11 and the supply node 12. When the operation signal Vop is at a low level, the gate-to-source voltage of the high side power PMOS transistor 11 may be higher than its threshold voltage, thereby turning on the high side power PMOS transistor 11. However, the great voltage difference across the resistor 15 may generate a current flowing through the resistor 15, which may adversely affect the inner control circuit of the high side power PMOS transistor 11.
FIG. 2 shows another conventional driver circuit 20 for driving a high side power PMOS transistor 21. As shown in FIG. 2, the high side power PMOS transistor 21 is coupled between a supply node 22 and an output node 23. A gate of the high side power PMOS transistor 21 is coupled to a control node 24 to receive an operation signal Vop. The driver circuit 20 comprises a current mirror 25 with a PMOS transistor 25a and a PMOS transistor 25b. Specifically, gates of the PMOS transistors 25a and 25b as well as the drain of transistor 25a are coupled to the supply node 22 via a resistor 26. The drain of the PMOS transistor 25a is coupled to receive a bias current from a current source 27 under the control of a switch 28, and a drain of the PMOS transistor 25b is coupled to the gate of the high side power PMOS transistor 21. A mirror current may be generated by the current mirror 25 based on the bias current from the current source 27 and then supplied to the gate of the high side power PMOS transistor 21.
In operation, when the switch 28 is turned on, the bias current may be supplied to the drain of 25a, thereby turning on the PMOS transistor 25b. Thus, the gate of the high side power MOS transistor 21 may be pulled up close to the supply voltage, and then the high side power MOS transistor 21 may be turned off. From the foregoing, a bias current is needed for the driver circuit 20 to turn off the high side power PMOS transistor 21, which significantly increases the shut-down power consumption of the driver circuit 20.
When the switch 28 is turned off, the PMOS transistor 25b is turned off because its gate is elevated to the supply voltage. Therefore, the operation of power transistor 21 is determined by the signal Vop.
FIG. 3 shows another conventional driver circuit 30 for driving a high side power PMOS transistor 31. As shown in FIG. 3, the high side power PMOS transistor 31 is coupled between a supply node 32 and an output node 33. A gate of the high side power MOS transistor 31 is coupled to a control node 34 to receive an operation signal Vop. The driver circuit 30 comprises a bipolar transistor 35 coupled between the supply node 32 and the gate of the high side power MOS transistor 31. A resistor 36 is coupled between a base and a collector of the bipolar transistor 35. The base of the bipolar transistor 35 and one end of the resistor 36 are coupled to a current source 37 through a switch 38. In operation, when the switch 38 is turned on to supply a bias current from the current source 37 to the resistor 36, the bipolar transistor 35 is quasi base-collector connected, thereby clamping a gate-to-source voltage of the high side power PMOS transistor 31 lower than a base-to-emitter voltage of the bipolar transistor 35. Thus, the high side power PMOS transistor 31 can be turned off if the bipolar transistor 35 has a lower threshold than the power PMOS transistor 31 in process. However, the manufacturing process of the bipolar transistor 35 may adversely affect the off state of the high side power PMOS transistor 31. Furthermore, the high side power PMOS transistor 31 may work under a sub-threshold state when the high side power PMOS transistor 31 is at a high temperature. Thus, the power consumption of the driver circuit 30 may be significantly increased due to a high leakage current flowing through the high side power PMOS transistor 31.